/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2024-07-03     huger       the first version
 */
#ifndef APPLICATIONS_BSP_BSP_H_
#define APPLICATIONS_BSP_BSP_H_

#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>


#include <string.h>
#include "typedef.h"


#include "ethercat_lan9252/applInterface.h"

#define Bank1_SRAM1_ADDR    ((u32)( 0x60000000))

// *****************************************************************************
// *****************************************************************************
// Section: File Scope or Global Data Types
// *****************************************************************************
// *****************************************************************************
#define CMD_SERIAL_READ 0x03
#define CMD_FAST_READ 0x0B
#define CMD_DUAL_OP_READ 0x3B
#define CMD_DUAL_IO_READ 0xBB
#define CMD_QUAD_OP_READ 0x6B
#define CMD_QUAD_IO_READ 0xEB
#define CMD_SERIAL_WRITE 0x02
#define CMD_DUAL_DATA_WRITE 0x32
#define CMD_DUAL_ADDR_DATA_WRITE 0xB2
#define CMD_QUAD_DATA_WRITE 0x62
#define CMD_QUAD_ADDR_DARA_WRITE 0xE2

#define CMD_SERIAL_READ_DUMMY 0
#define CMD_FAST_READ_DUMMY 1
#define CMD_DUAL_OP_READ_DUMMY 1
#define CMD_DUAL_IO_READ_DUMMY 2
#define CMD_QUAD_OP_READ_DUMMY 1
#define CMD_QUAD_IO_READ_DUMMY 4
#define CMD_SERIAL_WRITE_DUMMY 0
#define CMD_DUAL_DATA_WRITE_DUMMY 0
#define CMD_DUAL_ADDR_DATA_WRITE_DUMMY 0
#define CMD_QUAD_DATA_WRITE_DUMMY 0
#define CMD_QUAD_ADDR_DARA_WRITE_DUMMY 0

#define ESC_CSR_CMD_REG     0x304
#define ESC_CSR_DATA_REG    0x300
#define ESC_WRITE_BYTE      0x80
#define ESC_READ_BYTE       0xC0
#define ESC_CSR_BUSY        0x80

/*---------------------------------------------
-    Microcontroller definitions
-----------------------------------------------*/

///////////////////////////////////////////////////////////////////////////////
//9252 HW DEFINES
#define ECAT_REG_BASE_ADDR              0x0300

#define CSR_DATA_REG_OFFSET             0x00
#define CSR_CMD_REG_OFFSET              0x04
#define PRAM_READ_ADDR_LEN_OFFSET       0x08
#define PRAM_READ_CMD_OFFSET            0x0c
#define PRAM_WRITE_ADDR_LEN_OFFSET      0x10
#define PRAM_WRITE_CMD_OFFSET           0x14

#define PRAM_SPACE_AVBL_COUNT_MASK      0x1f
#define IS_PRAM_SPACE_AVBL_MASK         0x01

#define CSR_DATA_REG                    ECAT_REG_BASE_ADDR+CSR_DATA_REG_OFFSET
#define CSR_CMD_REG                     ECAT_REG_BASE_ADDR+CSR_CMD_REG_OFFSET
#define PRAM_READ_ADDR_LEN_REG          ECAT_REG_BASE_ADDR+PRAM_READ_ADDR_LEN_OFFSET
#define PRAM_READ_CMD_REG               ECAT_REG_BASE_ADDR+PRAM_READ_CMD_OFFSET
#define PRAM_WRITE_ADDR_LEN_REG         ECAT_REG_BASE_ADDR+PRAM_WRITE_ADDR_LEN_OFFSET
#define PRAM_WRITE_CMD_REG              ECAT_REG_BASE_ADDR+PRAM_WRITE_CMD_OFFSET

#define PRAM_READ_FIFO_REG              0x04
#define PRAM_WRITE_FIFO_REG             0x20

#define HBI_INDEXED_DATA0_REG           0x04
#define HBI_INDEXED_DATA1_REG           0x0c
#define HBI_INDEXED_DATA2_REG           0x14

#define HBI_INDEXED_INDEX0_REG          0x00
#define HBI_INDEXED_INDEX1_REG          0x08
#define HBI_INDEXED_INDEX2_REG          0x10

#define HBI_INDEXED_PRAM_READ_WRITE_FIFO    0x18

#define PRAM_RW_ABORT_MASK      (0x40000000)
#define PRAM_RW_BUSY_32B        (0x80000000)
#define PRAM_RW_BUSY_8B         (0x80)
#define PRAM_SET_READ           (0x40)
#define PRAM_SET_WRITE          0

typedef union
{
    u32 dword;
    u16 word[2];
    u8  byte[4];
}U32;


void MPU_Config(void);
void MX_FSMC_Init(void);
void Exit_IRQ_Init(void);     //irq中断
void Exit_SYNC0_Init(void);   //sync0 中断
void Exit_SYNC1_Init(void);   //sync1 中断

void PMPReadDRegister(u8 *ReadBuffer, u16 Address, u16 Count);
void PMPWriteRegister( u8 *WriteBuffer, u16 Address, u16 Count);
u32 PMPReadDWord (u16 Address);
void PMPWriteDWord (u16 Address, u32 Val);

void MX_TIM2_Init(void);

extern TIM_HandleTypeDef htim2;

#endif /* APPLICATIONS_BSP_BSP_H_ */
